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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-15 16:23:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-15 16:23:12 -0700 |
| commit | b29f26f6c7d880b9a446f6eacfa988c2018a1e30 (patch) | |
| tree | 1ce75cc63a4d9f24931501451a6b8a8ac204d7b5 /kernel/rtlil.cc | |
| parent | 5f00d335d4861fc03dd7b6cee68fd79505bd3d41 (diff) | |
| download | yosys-b29f26f6c7d880b9a446f6eacfa988c2018a1e30.tar.gz yosys-b29f26f6c7d880b9a446f6eacfa988c2018a1e30.tar.bz2 yosys-b29f26f6c7d880b9a446f6eacfa988c2018a1e30.zip | |
SigSpec::extend_u0() to return *this
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a09f4a0d1..ebb6f5bf6 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3426,7 +3426,7 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) check(); } -void RTLIL::SigSpec::extend_u0(int width, bool is_signed) +RTLIL::SigSpec& RTLIL::SigSpec::extend_u0(int width, bool is_signed) { cover("kernel.rtlil.sigspec.extend_u0"); @@ -3443,6 +3443,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) append(padding); } + return *this; } RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const |