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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:39:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:39:08 -0700 |
| commit | bbc0e06af3db4da924a3a92ced85adc87cf6abb6 (patch) | |
| tree | a96251669139f7026733d9583d766ce6b244a258 /kernel/rtlil.cc | |
| parent | d4212d128b5985cf09f5e7f14bc06e7323e644ac (diff) | |
| parent | 0acc51c3d82f65f73fa9e475c6fc41beabd925a6 (diff) | |
| download | yosys-bbc0e06af3db4da924a3a92ced85adc87cf6abb6.tar.gz yosys-bbc0e06af3db4da924a3a92ced85adc87cf6abb6.tar.bz2 yosys-bbc0e06af3db4da924a3a92ced85adc87cf6abb6.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ded1cd60e..bd2fd91a3 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3554,6 +3554,12 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const if (width_ != other.width_) return false; + // Without this, SigSpec() == SigSpec(State::S0, 0) will fail + // since the RHS will contain one SigChunk of width 0 causing + // the size check below to fail + if (width_ == 0) + return true; + pack(); other.pack(); |