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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-21 13:34:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-21 13:34:33 +0200 |
| commit | d7763634b68a735443c61aa32918ee0cdd6e9250 (patch) | |
| tree | d04a1d072d727d0776c42f68668785403cc92bf5 /kernel/rtlil.cc | |
| parent | 721f1f5ecfb6334904f6058d6d376d21b5efc438 (diff) | |
| download | yosys-d7763634b68a735443c61aa32918ee0cdd6e9250.tar.gz yosys-d7763634b68a735443c61aa32918ee0cdd6e9250.tar.bz2 yosys-d7763634b68a735443c61aa32918ee0cdd6e9250.zip | |
After reading the SV spec, using non-standard predict() instead of expect()
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 644a83a76..cf3c80604 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1017,7 +1017,7 @@ namespace { return; } - if (cell->type.in("$assert", "$assume", "$expect")) { + if (cell->type.in("$assert", "$assume", "$predict")) { port("\\A", 1); port("\\EN", 1); check_expected(); @@ -1798,7 +1798,7 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a RTLIL::Cell* RTLIL::Module::addExpect(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en) { - RTLIL::Cell *cell = addCell(name, "$expect"); + RTLIL::Cell *cell = addCell(name, "$predict"); cell->setPort("\\A", sig_a); cell->setPort("\\EN", sig_en); return cell; |