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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-28 10:52:58 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-28 10:52:58 +0200 |
| commit | d86a25f145012ccb6b2048af3aae22f13b97b505 (patch) | |
| tree | 7589225f762f11f108c61bbb6314a398032fbae5 /kernel/rtlil.cc | |
| parent | f99495a895eda0b1de6c1d7e8e1d5b1074316b34 (diff) | |
| download | yosys-d86a25f145012ccb6b2048af3aae22f13b97b505.tar.gz yosys-d86a25f145012ccb6b2048af3aae22f13b97b505.tar.bz2 yosys-d86a25f145012ccb6b2048af3aae22f13b97b505.zip | |
Added std::initializer_list<> constructor to SigSpec
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 610ab6a83..753c40090 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1652,6 +1652,18 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other) *this = other; } +RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts) +{ + cover("kernel.rtlil.sigspec.init.list"); + + width_ = 0; + hash_ = 0; + + std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end()); + for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++) + append(*it); +} + const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other) { cover("kernel.rtlil.sigspec.assign"); |