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| author | Sergey <37293587+SergeyDegtyar@users.noreply.github.com> | 2019-10-01 10:57:09 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-01 10:57:09 +0300 |
| commit | d99b1e32618f8aa92c01eb0ac5d08486f411cca0 (patch) | |
| tree | 5671ffa605b5f6b31b86aacb2dbeaacd018302d7 /kernel/rtlil.cc | |
| parent | fc56459746fec7751735749e3328378e1089b914 (diff) | |
| parent | d963e8c2c6207ad98d48dc528922ad58c030173f (diff) | |
| download | yosys-d99b1e32618f8aa92c01eb0ac5d08486f411cca0.tar.gz yosys-d99b1e32618f8aa92c01eb0ac5d08486f411cca0.tar.bz2 yosys-d99b1e32618f8aa92c01eb0ac5d08486f411cca0.zip | |
Merge branch 'master' into SergeyDegtyar/anlogic
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 1d380135b..ded1cd60e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1528,7 +1528,7 @@ std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const { std::vector<RTLIL::Cell*> result; - result.reserve(wires_.size()); + result.reserve(cells_.size()); for (auto &it : cells_) if (design->selected(this, it.second)) result.push_back(it.second); @@ -3083,6 +3083,7 @@ void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RT log_assert(other != NULL); log_assert(width_ == other->width_); + if (rules.empty()) return; unpack(); other->unpack(); @@ -3107,6 +3108,7 @@ void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules log_assert(other != NULL); log_assert(width_ == other->width_); + if (rules.empty()) return; unpack(); other->unpack(); |