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| author | Clifford Wolf <clifford@clifford.at> | 2014-01-03 02:43:31 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-03 02:43:31 +0100 |
| commit | eec2cd1e7850133302654ae8985d8ede9954a569 (patch) | |
| tree | f85d3a22d219a00fca9915e2594c637419155ada /kernel/rtlil.cc | |
| parent | fb2bf934dc6d2c969906b350c9a1b09a972bfdd7 (diff) | |
| download | yosys-eec2cd1e7850133302654ae8985d8ede9954a569.tar.gz yosys-eec2cd1e7850133302654ae8985d8ede9954a569.tar.bz2 yosys-eec2cd1e7850133302654ae8985d8ede9954a569.zip | |
Added RTLIL::SigSpec::optimized() API
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 1311f31cc..661525735 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1024,6 +1024,13 @@ void RTLIL::SigSpec::optimize() check(); } +RTLIL::SigSpec RTLIL::SigSpec::optimized() const +{ + RTLIL::SigSpec ret = *this; + ret.optimize(); + return ret; +} + bool RTLIL::SigChunk::compare(const RTLIL::SigChunk &a, const RTLIL::SigChunk &b) { if (a.wire != b.wire) { |