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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-18 10:58:47 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-18 10:58:47 +0200 |
| commit | f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c (patch) | |
| tree | 1778829a6932d18730a3a085a80a65205189c7ba /kernel/rtlil.cc | |
| parent | 24a5c6585678f89058382fe2c3f36b821b419e90 (diff) | |
| parent | 736105b0468f9468f00915cad60949535ce5a496 (diff) | |
| download | yosys-f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c.tar.gz yosys-f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c.tar.bz2 yosys-f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c.zip | |
Merge pull request #659 from rubund/sv_interfaces
Support for SystemVerilog interfaces and modports
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a4fa2cf04..14259f8ed 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -639,6 +639,11 @@ RTLIL::Module::~Module() delete it->second; } +void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>) +{ + log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name)); +} + RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail) { if (mayfail) @@ -646,6 +651,14 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLI log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name)); } + +RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail) +{ + if (mayfail) + return RTLIL::IdString(); + log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name)); +} + size_t RTLIL::Module::count_id(RTLIL::IdString id) { return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id); |