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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:18:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:18:01 -0700 |
| commit | f374e0ab7e9a91fa86814b0f750660e92ed16ae6 (patch) | |
| tree | ae525a0ffa0e9588c833cf864f1eea62436afa4f /kernel/rtlil.cc | |
| parent | 4e8f0fbce84db96f8cd3d4e1594b30cbc8ec1020 (diff) | |
| parent | 477e566e8d203ec7754c90fc845d7f3f759f2974 (diff) | |
| download | yosys-f374e0ab7e9a91fa86814b0f750660e92ed16ae6.tar.gz yosys-f374e0ab7e9a91fa86814b0f750660e92ed16ae6.tar.bz2 yosys-f374e0ab7e9a91fa86814b0f750660e92ed16ae6.zip | |
Merge remote-tracking branch 'origin/master' into xc7mux
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 3990ec283..94dbf31c0 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1381,7 +1381,34 @@ void RTLIL::Module::check() for (auto &it : processes) { log_assert(it.first == it.second->name); log_assert(!it.first.empty()); - // FIXME: More checks here.. + log_assert(it.second->root_case.compare.empty()); + std::vector<CaseRule*> all_cases = {&it.second->root_case}; + for (size_t i = 0; i < all_cases.size(); i++) { + for (auto &switch_it : all_cases[i]->switches) { + for (auto &case_it : switch_it->cases) { + for (auto &compare_it : case_it->compare) { + log_assert(switch_it->signal.size() == compare_it.size()); + } + all_cases.push_back(case_it); + } + } + } + for (auto &sync_it : it.second->syncs) { + switch (sync_it->type) { + case SyncType::ST0: + case SyncType::ST1: + case SyncType::STp: + case SyncType::STn: + case SyncType::STe: + log_assert(!sync_it->signal.empty()); + break; + case SyncType::STa: + case SyncType::STg: + case SyncType::STi: + log_assert(sync_it->signal.empty()); + break; + } + } } for (auto &it : connections_) { |