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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-01 16:26:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-01 16:26:43 -0700 |
| commit | f86d153cef724af9d30e4139783a7e14d7ba0a19 (patch) | |
| tree | 1c2cd09407cbeef2f68c19f9bcfb95566355fa01 /kernel/rtlil.cc | |
| parent | acafcdc94dc148b2bf9c8faef173e5b2b54e1ac5 (diff) | |
| parent | 7a0af004a0a4dc3831997f0845d40fc3ea514281 (diff) | |
| download | yosys-f86d153cef724af9d30e4139783a7e14d7ba0a19.tar.gz yosys-f86d153cef724af9d30e4139783a7e14d7ba0a19.tar.bz2 yosys-f86d153cef724af9d30e4139783a7e14d7ba0a19.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7e1159cac..dd6817873 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3456,7 +3456,7 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const pack(); other.pack(); - if (chunks_.size() != chunks_.size()) + if (chunks_.size() != other.chunks_.size()) return false; updhash(); |