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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-07 16:53:28 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-07 16:53:28 +0100 |
| commit | 0e1661f84e99f1d4a487e7a432b05a6cb2071714 (patch) | |
| tree | 9862950a7c92069d88e590da6d0a97bf7b7eb95f /kernel/rtlil.h | |
| parent | ed4bcd52e5d7ab466a4bcd87ae787f1ab7c70fb7 (diff) | |
| download | yosys-0e1661f84e99f1d4a487e7a432b05a6cb2071714.tar.gz yosys-0e1661f84e99f1d4a487e7a432b05a6cb2071714.tar.bz2 yosys-0e1661f84e99f1d4a487e7a432b05a6cb2071714.zip | |
Fixed type of sign extension in opt_const $eq/$ne handling
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 6cb471b58..376a09abf 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -342,6 +342,7 @@ struct RTLIL::SigSpec { void append(const RTLIL::SigSpec &signal); bool combine(RTLIL::SigSpec signal, RTLIL::State freeState = RTLIL::State::Sz, bool override = false); void extend(int width, bool is_signed = false); + void extend_un0(int width, bool is_signed = false); void check() const; bool operator <(const RTLIL::SigSpec &other) const; bool operator ==(const RTLIL::SigSpec &other) const; |