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author | Rupert Swarbrick <rswarbrick@gmail.com> | 2020-05-22 16:59:24 +0100 |
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committer | Rupert Swarbrick <rswarbrick@gmail.com> | 2020-05-26 13:18:01 +0100 |
commit | 17b5f23f20d6cadc8ce6220e457880720aae4866 (patch) | |
tree | 7ee9118717e9ba7302d88ddd3571542262335dbb /kernel/rtlil.h | |
parent | a7f2ef6d34c4b336a910b3c6f3d2cc11da8a82b4 (diff) | |
download | yosys-17b5f23f20d6cadc8ce6220e457880720aae4866.tar.gz yosys-17b5f23f20d6cadc8ce6220e457880720aae4866.tar.bz2 yosys-17b5f23f20d6cadc8ce6220e457880720aae4866.zip |
Use default copy constructor for RTLIL::SigBit
There was a handwritten copy constructor, which I'm not sure was
actually legal C++ (it unconditionally read from the 'data' member of
a union, which wouldn't have been written if wire was true). It was
also a bit less efficient than the constructor you get from the
compiler by default (which is allowed to just copy the memory).
This gives a marginal (~0.25%) decrease in code size when compiled
with GCC 9.3.
Diffstat (limited to 'kernel/rtlil.h')
-rw-r--r-- | kernel/rtlil.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 11c45bbec..4a23a2d06 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -721,7 +721,7 @@ struct RTLIL::SigBit SigBit(const RTLIL::SigChunk &chunk); SigBit(const RTLIL::SigChunk &chunk, int index); SigBit(const RTLIL::SigSpec &sig); - SigBit(const RTLIL::SigBit &sigbit); + SigBit(const RTLIL::SigBit &sigbit) = default; RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default; bool operator <(const RTLIL::SigBit &other) const; @@ -1494,7 +1494,6 @@ inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_as inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); } inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; } inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; } -inline RTLIL::SigBit::SigBit(const RTLIL::SigBit &sigbit) : wire(sigbit.wire), data(sigbit.data){ if (wire) offset = sigbit.offset; } inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const { if (wire == other.wire) |