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author | Ahmed Irfan <irfan@ubuntu.(none)> | 2014-01-18 18:10:31 +0100 |
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committer | Ahmed Irfan <irfan@ubuntu.(none)> | 2014-01-18 18:10:31 +0100 |
commit | 1dd797ab09d2fb6a4ab903cfa050fa51cfcc6dcd (patch) | |
tree | 3c254e7a3ca11831e463d9a4ce88b5aea0677952 /kernel/rtlil.h | |
parent | 66198d8591a66b8ec34237c1151d992c7f4d5224 (diff) | |
parent | bef17eeb109dd2dc4eaba6eb808a0172c0c53265 (diff) | |
download | yosys-1dd797ab09d2fb6a4ab903cfa050fa51cfcc6dcd.tar.gz yosys-1dd797ab09d2fb6a4ab903cfa050fa51cfcc6dcd.tar.bz2 yosys-1dd797ab09d2fb6a4ab903cfa050fa51cfcc6dcd.zip |
Merge branch 'master' of https://github.com/cliffordwolf/yosys
Diffstat (limited to 'kernel/rtlil.h')
-rw-r--r-- | kernel/rtlil.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 504fdbbdc..e0b3a693d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -227,6 +227,9 @@ struct RTLIL::Selection { if (!full_selection && selected_modules.count(module->name) == 0) selected_members[module->name].insert(member->name); } + bool empty() const { + return !full_selection && selected_modules.empty() && selected_members.empty(); + } }; struct RTLIL::Design { |