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| author | Clifford Wolf <clifford@clifford.at> | 2013-06-19 09:30:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-06-19 09:30:37 +0200 |
| commit | 21e38bed98d3d6bc4ae5833f6f609ac8f12d6361 (patch) | |
| tree | 059c694e9a587cfe77f30297e7a7fcc7ba11b6c8 /kernel/rtlil.h | |
| parent | a046a302f0d258dccc4fd22cb341f41bacf0aaba (diff) | |
| download | yosys-21e38bed98d3d6bc4ae5833f6f609ac8f12d6361.tar.gz yosys-21e38bed98d3d6bc4ae5833f6f609ac8f12d6361.tar.bz2 yosys-21e38bed98d3d6bc4ae5833f6f609ac8f12d6361.zip | |
Added "eval" pass
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 5ababa7ec..6dde475d1 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -327,6 +327,7 @@ struct RTLIL::SigSpec { std::string as_string() const; RTLIL::Const as_const() const; bool match(std::string pattern) const; + static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); }; struct RTLIL::CaseRule { |