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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-09 12:02:27 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-09 12:02:27 +0100 |
| commit | 223892ac286b1dd0d09bf2449cd8953b1029ae68 (patch) | |
| tree | 704ff413b0dd4112106b7dca8fa5761236700019 /kernel/rtlil.h | |
| parent | 2864cb3b59d1e293d3738eebbaf363b4e03d365e (diff) | |
| download | yosys-223892ac286b1dd0d09bf2449cd8953b1029ae68.tar.gz yosys-223892ac286b1dd0d09bf2449cd8953b1029ae68.tar.bz2 yosys-223892ac286b1dd0d09bf2449cd8953b1029ae68.zip | |
Improved user-friendliness of "sat" and "eval" expression parsing
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 7628bf0a8..952cb5944 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -357,6 +357,7 @@ struct RTLIL::SigSpec { RTLIL::Const as_const() const; bool match(std::string pattern) const; static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); }; struct RTLIL::CaseRule { |