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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-23 16:16:06 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-23 16:16:06 +0100 |
| commit | 245724a504528156485bbb32710b5e5444899ce1 (patch) | |
| tree | 0f40d2aad76556901949dff62905a2eb7e40b331 /kernel/rtlil.h | |
| parent | 6dad1913779f729222f65e1098a4facb36c5837a (diff) | |
| parent | 18291c20d2b17689729d9c36b08967e928e4e32a (diff) | |
| download | yosys-245724a504528156485bbb32710b5e5444899ce1.tar.gz yosys-245724a504528156485bbb32710b5e5444899ce1.tar.bz2 yosys-245724a504528156485bbb32710b5e5444899ce1.zip | |
Merge pull request #761 from whitequark/proc_clean_partial
proc_clean: remove any empty cases, if possible to do safely
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 276540aa1..f877622aa 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1227,6 +1227,8 @@ struct RTLIL::CaseRule ~CaseRule(); void optimize(); + bool empty() const; + template<typename T> void rewrite_sigspecs(T &functor); RTLIL::CaseRule *clone() const; }; @@ -1238,6 +1240,8 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject ~SwitchRule(); + bool empty() const; + template<typename T> void rewrite_sigspecs(T &functor); RTLIL::SwitchRule *clone() const; }; |