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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 21:34:14 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 21:34:14 +0200 |
| commit | 2a41afb7b2415f824ea1f60337050c9f41c0e33f (patch) | |
| tree | af7db353746c8177ffa374ba2667b3fac850bc48 /kernel/rtlil.h | |
| parent | 20a7965f61a43b8c367b1042081a57b5a4005b33 (diff) | |
| download | yosys-2a41afb7b2415f824ea1f60337050c9f41c0e33f.tar.gz yosys-2a41afb7b2415f824ea1f60337050c9f41c0e33f.tar.bz2 yosys-2a41afb7b2415f824ea1f60337050c9f41c0e33f.zip | |
Added RTLIL::SigSpec::repeat()
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a13164c37..95de5f8c6 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -565,6 +565,8 @@ public: void extend(int width, bool is_signed = false); void extend_u0(int width, bool is_signed = false); + RTLIL::SigSpec repeat(int num) const; + bool operator <(const RTLIL::SigSpec &other) const; bool operator ==(const RTLIL::SigSpec &other) const; inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); } |