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| author | Clifford Wolf <clifford@clifford.at> | 2013-08-09 15:20:22 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-08-09 15:20:22 +0200 |
| commit | 376150c9265e01a7b012d716db0325af3776b6b0 (patch) | |
| tree | 77690e4929113ad3d227969c7d1e8a4ad4923169 /kernel/rtlil.h | |
| parent | 05483619f0b776eda2f96ca7a9bfb8cdc3732a0e (diff) | |
| download | yosys-376150c9265e01a7b012d716db0325af3776b6b0.tar.gz yosys-376150c9265e01a7b012d716db0325af3776b6b0.tar.bz2 yosys-376150c9265e01a7b012d716db0325af3776b6b0.zip | |
Added techmap -opt mode
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 4a4e82356..7796ce969 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -199,6 +199,10 @@ struct RTLIL::Selection { bool selected_whole_module(RTLIL::IdString mod_name) const; bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; void optimize(RTLIL::Design *design); + template<typename T1, typename T2> void select(T1 *module, T2 *member) { + if (!full_selection && selected_modules.count(module->name) == 0) + selected_members[module->name].insert(member->name); + } }; struct RTLIL::Design { @@ -221,8 +225,7 @@ struct RTLIL::Design { template<typename T1, typename T2> void select(T1 *module, T2 *member) { if (selection_stack.size() > 0) { RTLIL::Selection &sel = selection_stack.back(); - if (!sel.full_selection && sel.selected_modules.count(module->name) == 0) - sel.selected_members.at(module->name).insert(member->name); + sel.select(module, member); } } }; |