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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-05 14:47:03 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-05 14:47:03 +0200 |
| commit | 523df7314502e2674df5287289dcf8eb204c17ac (patch) | |
| tree | 4f4f73b3bd27e992d543672b551b77eaa7f1d9c0 /kernel/rtlil.h | |
| parent | d3b1a29708fc9cfd793180763484125a5f978d1a (diff) | |
| download | yosys-523df7314502e2674df5287289dcf8eb204c17ac.tar.gz yosys-523df7314502e2674df5287289dcf8eb204c17ac.tar.bz2 yosys-523df7314502e2674df5287289dcf8eb204c17ac.zip | |
Added support for truncating of wires to wreduce pass
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 8dfcbcaa0..8ec599417 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -590,6 +590,10 @@ public: std::vector<RTLIL::Wire*> selected_wires() const; std::vector<RTLIL::Cell*> selected_cells() const; + template<typename T> bool selected(T *member) const { + return design->selected_member(name, member->name); + } + RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } @@ -604,6 +608,9 @@ public: void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); + void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); + void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); + RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); |