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| author | Clifford Wolf <clifford@clifford.at> | 2016-10-14 12:33:56 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-10-14 12:33:56 +0200 |
| commit | 53655d173b2928328061c8440cc993508e951e1f (patch) | |
| tree | 87c12bdeb1a7cde96569efd1da18bee909b2f115 /kernel/rtlil.h | |
| parent | ffbb4e992e5312d8feafcc1c6c850ea06c3e09b2 (diff) | |
| download | yosys-53655d173b2928328061c8440cc993508e951e1f.tar.gz yosys-53655d173b2928328061c8440cc993508e951e1f.tar.bz2 yosys-53655d173b2928328061c8440cc993508e951e1f.zip | |
Added $global_clock verilog syntax support for creating $ff cells
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 058f6acf4..109e33351 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -42,7 +42,8 @@ namespace RTLIL STn = 3, // edge sensitive: negedge STe = 4, // edge sensitive: both edges STa = 5, // always active - STi = 6 // init + STg = 6, // global clock + STi = 7 // init }; enum ConstFlags : unsigned char { |