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| author | Jannis Harder <me@jix.one> | 2022-08-16 14:18:35 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-16 14:18:35 +0200 |
| commit | 556d008ed3c2db351e93e0075ccd47bdfb634fd9 (patch) | |
| tree | ab23fa7355df8f8ead24839ee7846e68cdbfb935 /kernel/rtlil.h | |
| parent | c26b2bf543a226e65a3fb07040bb278d668accf2 (diff) | |
| parent | f7023d06a2bda56467c8f07cc44d3b92f0eab2ba (diff) | |
| download | yosys-556d008ed3c2db351e93e0075ccd47bdfb634fd9.tar.gz yosys-556d008ed3c2db351e93e0075ccd47bdfb634fd9.tar.bz2 yosys-556d008ed3c2db351e93e0075ccd47bdfb634fd9.zip | |
Merge pull request #3434 from jix/witness_flow
Updated formal flow with new witness format
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index db175d7e9..27ffdff1f 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1375,6 +1375,8 @@ public: RTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + RTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = ""); + // The methods without the add* prefix create a cell and an output signal. They return the newly created output signal. RTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = ""); |