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author | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 09:47:08 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 09:48:11 -0700 |
commit | 5b81df57c8c6779077c69ed8247fce7647616ade (patch) | |
tree | c7d7313dbec3619e8e3329c992f3f7594ab750bb /kernel/rtlil.h | |
parent | ae11156c90eec958cd9ab631a28c41eccc105e56 (diff) | |
download | yosys-5b81df57c8c6779077c69ed8247fce7647616ade.tar.gz yosys-5b81df57c8c6779077c69ed8247fce7647616ade.tar.bz2 yosys-5b81df57c8c6779077c69ed8247fce7647616ade.zip |
xilinx: tidy up cells_sim.v a little
Diffstat (limited to 'kernel/rtlil.h')
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