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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-18 12:47:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-18 12:47:12 -0700 |
| commit | 7324a4c2cd0132f792f4fade1a77aeceae46bd85 (patch) | |
| tree | 4510f12308d725eeeac2b2635cf73dc08823f80c /kernel/rtlil.h | |
| parent | 6a4025b5eef3ea96a8a7cdb0046cb2193cfa08e5 (diff) | |
| download | yosys-7324a4c2cd0132f792f4fade1a77aeceae46bd85.tar.gz yosys-7324a4c2cd0132f792f4fade1a77aeceae46bd85.tar.bz2 yosys-7324a4c2cd0132f792f4fade1a77aeceae46bd85.zip | |
Remove iterator based Module::remove as per @cliffordwolf
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 4a0f8b4f8..f4fcf5dcf 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1040,7 +1040,6 @@ public: // Removing wires is expensive. If you have to remove wires, remove them all at once. void remove(const pool<RTLIL::Wire*> &wires); void remove(RTLIL::Cell *cell); - dict<RTLIL::IdString, RTLIL::Cell*>::iterator remove(dict<RTLIL::IdString, RTLIL::Cell*>::iterator it); void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); |