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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-09 16:56:29 +0200 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-07-09 18:48:38 +0100 |
| commit | 76f20492a468ffef9902712e36c856f3a6e63dd5 (patch) | |
| tree | 87ac4c63577e7f0ca026fcd0a0e89fec3e0d5803 /kernel/rtlil.h | |
| parent | 17e0cc010c12fc69fdadc2c342da1ef8e16a2d91 (diff) | |
| download | yosys-76f20492a468ffef9902712e36c856f3a6e63dd5.tar.gz yosys-76f20492a468ffef9902712e36c856f3a6e63dd5.tar.bz2 yosys-76f20492a468ffef9902712e36c856f3a6e63dd5.zip | |
Merge pull request #1162 from whitequark/rtlil-case-attrs
Allow attributes on individual switch cases in RTLIL
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 8509670ff..7b7367fba 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1315,7 +1315,7 @@ public: #endif }; -struct RTLIL::CaseRule +struct RTLIL::CaseRule : public RTLIL::AttrObject { std::vector<RTLIL::SigSpec> compare; std::vector<RTLIL::SigSig> actions; |