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| author | Robert Baruch <robert.c.baruch@gmail.com> | 2021-02-20 11:46:30 -0800 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:52:43 +0100 |
| commit | 7c50b89b244ed23d42f95c3d08efde40ec7ddd82 (patch) | |
| tree | 4d68ecb3ee14380fe5482aea72d6b69cb35a9e00 /kernel/rtlil.h | |
| parent | ae07298a6b26315793167d9fe0e47d33412fc033 (diff) | |
| download | yosys-7c50b89b244ed23d42f95c3d08efde40ec7ddd82.tar.gz yosys-7c50b89b244ed23d42f95c3d08efde40ec7ddd82.tar.bz2 yosys-7c50b89b244ed23d42f95c3d08efde40ec7ddd82.zip | |
Adds is_wire to SigBit and SigChunk
Useful for PYOSYS because Python can't easily check wire against NULL.
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 4dad3c428..a5f170085 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -735,6 +735,7 @@ struct RTLIL::SigChunk RTLIL::SigChunk extract(int offset, int length) const; inline int size() const { return width; } + inline int is_wire() const { return wire != NULL; } bool operator <(const RTLIL::SigChunk &other) const; bool operator ==(const RTLIL::SigChunk &other) const; @@ -760,6 +761,8 @@ struct RTLIL::SigBit SigBit(const RTLIL::SigBit &sigbit) = default; RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default; + inline int is_wire() const { return wire != NULL; } + bool operator <(const RTLIL::SigBit &other) const; bool operator ==(const RTLIL::SigBit &other) const; bool operator !=(const RTLIL::SigBit &other) const; |