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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-29 11:19:21 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-29 11:19:21 +0100 |
| commit | 88af5b6a162ebc4fcc753794b38491e7897b702a (patch) | |
| tree | dbf51c9f01b4bb7fe5224d0f558d6bc4ce09c867 /kernel/rtlil.h | |
| parent | 0d48b846ac8ed74b607fc4706e742a45ab86f2dd (diff) | |
| download | yosys-88af5b6a162ebc4fcc753794b38491e7897b702a.tar.gz yosys-88af5b6a162ebc4fcc753794b38491e7897b702a.tar.bz2 yosys-88af5b6a162ebc4fcc753794b38491e7897b702a.zip | |
Improved opt_share for reduce cells
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a0d7a1a37..fe88182fa 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -277,6 +277,7 @@ struct RTLIL::SigChunk { bool operator <(const RTLIL::SigChunk &other) const; bool operator ==(const RTLIL::SigChunk &other) const; bool operator !=(const RTLIL::SigChunk &other) const; + static bool compare(const RTLIL::SigChunk &a, const RTLIL::SigChunk &b); }; struct RTLIL::SigSpec { @@ -291,6 +292,7 @@ struct RTLIL::SigSpec { SigSpec(RTLIL::State bit, int width = 1); void expand(); void optimize(); + void sort(); void sort_and_unify(); void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const; |