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| author | whitequark <whitequark@whitequark.org> | 2020-06-09 12:41:02 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-09 12:41:02 +0000 |
| commit | 9a2cf5e3db15218af9a5320a8ca1a7f190aa236b (patch) | |
| tree | a185df7153771283b6b9afb17ad918bdea60adac /kernel/rtlil.h | |
| parent | 3dc32490e071f221481c7bae9285957565026d76 (diff) | |
| parent | 98e108034561bb3a9276594ebef2f80da38748ad (diff) | |
| download | yosys-9a2cf5e3db15218af9a5320a8ca1a7f190aa236b.tar.gz yosys-9a2cf5e3db15218af9a5320a8ca1a7f190aa236b.tar.bz2 yosys-9a2cf5e3db15218af9a5320a8ca1a7f190aa236b.zip | |
Merge pull request #2128 from whitequark/flatten-processes
flatten: accept processes
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f751bdce4..f3dc3af68 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1175,6 +1175,8 @@ public: RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other); + RTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other); + // The add* methods create a cell and return the created cell. All signals must exist in advance. RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); |