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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 19:56:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | a233762a815fc180b371f699e865a7d7aed77bca (patch) | |
| tree | 722e54921bbc09595c046c6045cd531445945fc9 /kernel/rtlil.h | |
| parent | 3b5f4ff39c94a5a664043f35b95a50240ffe9d12 (diff) | |
| download | yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.gz yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.bz2 yosys-a233762a815fc180b371f699e865a7d7aed77bca.zip | |
SigSpec refactoring: renamed chunks and width to __chunks and __width
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 9b3e44179..0919b3926 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -496,8 +496,11 @@ struct RTLIL::SigBit { }; struct RTLIL::SigSpec { - std::vector<RTLIL::SigChunk> chunks; // LSB at index 0 - int width; +public: + std::vector<RTLIL::SigChunk> __chunks; // LSB at index 0 + int __width; + +public: SigSpec(); SigSpec(const RTLIL::Const &data); SigSpec(const RTLIL::SigChunk &chunk); @@ -551,8 +554,8 @@ struct RTLIL::SigSpec { }; inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { - assert(sig.width == 1 && sig.chunks.size() == 1); - *this = SigBit(sig.chunks[0]); + assert(sig.__width == 1 && sig.__chunks.size() == 1); + *this = SigBit(sig.__chunks[0]); } struct RTLIL::CaseRule { |