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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-12 15:55:54 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-12 16:00:34 -0700 |
| commit | b567f03c266b0c44d81a24dde2ed538f1db05d4e (patch) | |
| tree | 60e52f1a3738d85e8c9d55058abfe17eac41859c /kernel/rtlil.h | |
| parent | a076052fe423e262e00e75756f5f1b24ea461783 (diff) | |
| download | yosys-b567f03c266b0c44d81a24dde2ed538f1db05d4e.tar.gz yosys-b567f03c266b0c44d81a24dde2ed538f1db05d4e.tar.bz2 yosys-b567f03c266b0c44d81a24dde2ed538f1db05d4e.zip | |
kernel: optimise Module::remove(const pool<RTLIL::Wire*>()
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 58c5d9674..451bdd7b6 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -758,6 +758,10 @@ private: unpack(); } + // Only used by Module::remove(const pool<Wire*> &wires) + // but cannot be more specific as it isn't yet declared + friend struct RTLIL::Module; + public: SigSpec(); SigSpec(const RTLIL::SigSpec &other); |