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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-25 14:23:10 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-25 14:23:10 +0200 |
| commit | c762050e7fc2c733210f8cd2b147e6084af0afe1 (patch) | |
| tree | 3b3cc389fc31cd90eebd036f3d5a1b3e3acc74fa /kernel/rtlil.h | |
| parent | 1834af5e5382de67860f5714746566123c4d6b53 (diff) | |
| download | yosys-c762050e7fc2c733210f8cd2b147e6084af0afe1.tar.gz yosys-c762050e7fc2c733210f8cd2b147e6084af0afe1.tar.bz2 yosys-c762050e7fc2c733210f8cd2b147e6084af0afe1.zip | |
Added RTLIL::SigSpec is_chunk()/as_chunk() API
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a4b7e8492..59db099fb 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -577,6 +577,8 @@ public: inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); } bool is_wire() const; + bool is_chunk() const; + bool is_fully_const() const; bool is_fully_def() const; bool is_fully_undef() const; @@ -587,6 +589,7 @@ public: std::string as_string() const; RTLIL::Const as_const() const; RTLIL::Wire *as_wire() const; + RTLIL::SigChunk as_chunk() const; bool match(std::string pattern) const; |