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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-18 13:25:24 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-18 13:25:24 +0200 |
| commit | cc5e379eca3cea2369c49ebf8e554b35614495de (patch) | |
| tree | 71e6cd45aca3d4e28332ed60b9bf5059f037889e /kernel/rtlil.h | |
| parent | 0836a1f2ba3990fff81b353adfe93cfd35ae7246 (diff) | |
| download | yosys-cc5e379eca3cea2369c49ebf8e554b35614495de.tar.gz yosys-cc5e379eca3cea2369c49ebf8e554b35614495de.tar.bz2 yosys-cc5e379eca3cea2369c49ebf8e554b35614495de.zip | |
Added RTLIL NEW_WIRE macro
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 7796ce969..a3d1dafd9 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -129,6 +129,9 @@ namespace RTLIL #define NEW_ID \ RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__) +#define NEW_WIRE(_mod, _width) \ + (_mod)->new_wire(_width, NEW_ID) + template <typename T> struct sort_by_name { bool operator()(T *a, T *b) const { return a->name < b->name; @@ -244,6 +247,7 @@ struct RTLIL::Module { virtual size_t count_id(RTLIL::IdString id); virtual void check(); virtual void optimize(); + RTLIL::SigSpec new_wire(int width, RTLIL::IdString name); void add(RTLIL::Wire *wire); void add(RTLIL::Cell *cell); void fixup_ports(); |