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author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 14:34:12 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 14:45:14 +0200 |
commit | cd9407404a7bf3a5b8735af00c8f13ff97ac1495 (patch) | |
tree | 239959b3e687983895a71f2bc6b10e4daa64c555 /kernel/rtlil.h | |
parent | e6d33513a5b809facc6e3e5e75d2248bfa94f82b (diff) | |
download | yosys-cd9407404a7bf3a5b8735af00c8f13ff97ac1495.tar.gz yosys-cd9407404a7bf3a5b8735af00c8f13ff97ac1495.tar.bz2 yosys-cd9407404a7bf3a5b8735af00c8f13ff97ac1495.zip |
Added RTLIL::Monitor
Diffstat (limited to 'kernel/rtlil.h')
-rw-r--r-- | kernel/rtlil.h | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 1163dccef..5107e5f2b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -54,6 +54,7 @@ namespace RTLIL struct Const; struct Selection; + struct Monitor; struct Design; struct Module; struct Wire; @@ -328,8 +329,20 @@ struct RTLIL::Selection } }; +struct RTLIL::Monitor +{ + virtual void notify_module_add(RTLIL::Module*) { } + virtual void notify_module_del(RTLIL::Module*) { } + virtual void notify_cell_connect(RTLIL::Cell*, const std::pair<RTLIL::IdString, RTLIL::SigSpec>&) { } + virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { } + virtual void notify_new_connections(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { } + virtual void notify_blackout(RTLIL::Module*) { } +}; + struct RTLIL::Design { + std::set<RTLIL::Monitor*> monitors; + int refcount_modules_; std::map<RTLIL::IdString, RTLIL::Module*> modules_; @@ -404,6 +417,8 @@ protected: public: RTLIL::Design *design; + std::set<RTLIL::Monitor*> monitors; + int refcount_wires_; int refcount_cells_; @@ -426,6 +441,7 @@ public: void connect(const RTLIL::SigSig &conn); void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); + void new_connections(const std::vector<RTLIL::SigSig> &new_conn); const std::vector<RTLIL::SigSig> &connections() const; void fixup_ports(); @@ -631,7 +647,7 @@ struct RTLIL::Cell protected: // use module->addCell() and module->remove() to create or destroy cells friend struct RTLIL::Module; - Cell() { }; + Cell() : module(nullptr) { }; ~Cell() { }; public: @@ -647,7 +663,7 @@ public: RTLIL_ATTRIBUTE_MEMBERS // access cell ports - bool has(RTLIL::IdString portname); + bool has(RTLIL::IdString portname) const; void unset(RTLIL::IdString portname); void set(RTLIL::IdString portname, RTLIL::SigSpec signal); const RTLIL::SigSpec &get(RTLIL::IdString portname) const; |