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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-07 14:27:35 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-07 14:27:35 +0200 |
| commit | e9a756aa7a8831e644b36cfb6731e5629adc3dc6 (patch) | |
| tree | 6e541a18375563445ccb679b923822c279795465 /kernel/rtlil.h | |
| parent | 48f7682e32a3aead82b304c3d13fa47920e128c0 (diff) | |
| parent | 2d1b517b01b6cd1ec35018d4c63aaa091fcc1917 (diff) | |
| download | yosys-e9a756aa7a8831e644b36cfb6731e5629adc3dc6.tar.gz yosys-e9a756aa7a8831e644b36cfb6731e5629adc3dc6.tar.bz2 yosys-e9a756aa7a8831e644b36cfb6731e5629adc3dc6.zip | |
Merge pull request #1213 from YosysHQ/eddie/wreduce_add
wreduce/opt_expr: improve width reduction for $add and $sub cells
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 1cfe71473..c07d39c65 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -788,6 +788,7 @@ public: RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; RTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const; RTLIL::SigSpec extract(int offset, int length = 1) const; + RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); } void append(const RTLIL::SigSpec &signal); void append_bit(const RTLIL::SigBit &bit); @@ -834,6 +835,7 @@ public: operator std::vector<RTLIL::SigChunk>() const { return chunks(); } operator std::vector<RTLIL::SigBit>() const { return bits(); } + RTLIL::SigBit at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; } unsigned int hash() const { if (!hash_) updhash(); return hash_; }; |