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author | Clifford Wolf <clifford@clifford.at> | 2018-10-18 10:58:47 +0200 |
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committer | GitHub <noreply@github.com> | 2018-10-18 10:58:47 +0200 |
commit | f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c (patch) | |
tree | 1778829a6932d18730a3a085a80a65205189c7ba /kernel/rtlil.h | |
parent | 24a5c6585678f89058382fe2c3f36b821b419e90 (diff) | |
parent | 736105b0468f9468f00915cad60949535ce5a496 (diff) | |
download | yosys-f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c.tar.gz yosys-f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c.tar.bz2 yosys-f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c.zip |
Merge pull request #659 from rubund/sv_interfaces
Support for SystemVerilog interfaces and modports
Diffstat (limited to 'kernel/rtlil.h')
-rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 027faf416..276540aa1 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -907,7 +907,9 @@ public: Module(); virtual ~Module(); virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail = false); + virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail = false); virtual size_t count_id(RTLIL::IdString id); + virtual void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces); virtual void sort(); virtual void check(); |