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authorEddie Hung <eddie@fpgeh.com>2020-03-26 14:33:06 -0700
committerEddie Hung <eddie@fpgeh.com>2020-03-26 14:33:06 -0700
commitf97b90e40b9a9b8e8b8ea692c651464980721ce4 (patch)
tree5cf78a4af1a31ecb46799c93664c178f69203e6b /kernel/rtlil.h
parent940640ac4472a83fb575838e66cceeedcb785b61 (diff)
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kernel: Cell::set{Port,Param}() to pass by value, but use std::move
Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
Diffstat (limited to 'kernel/rtlil.h')
-rw-r--r--kernel/rtlil.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index deb677f68..c0f1c7fa8 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1381,7 +1381,7 @@ public:
// access cell ports
bool hasPort(RTLIL::IdString portname) const;
void unsetPort(RTLIL::IdString portname);
- void setPort(RTLIL::IdString portname, const RTLIL::SigSpec &signal);
+ void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal);
const RTLIL::SigSpec &getPort(RTLIL::IdString portname) const;
const dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;
@@ -1393,7 +1393,7 @@ public:
// access cell parameters
bool hasParam(RTLIL::IdString paramname) const;
void unsetParam(RTLIL::IdString paramname);
- void setParam(RTLIL::IdString paramname, const RTLIL::Const& value);
+ void setParam(RTLIL::IdString paramname, RTLIL::Const value);
const RTLIL::Const &getParam(RTLIL::IdString paramname) const;
void sort();