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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-06 19:22:46 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-06 19:22:46 +0100 |
| commit | fa295a4528513d6beeff638520d519faafd99324 (patch) | |
| tree | b11afcff018bdb515596ec4b89dac9ff6a514931 /kernel/rtlil.h | |
| parent | d4b0f28881e361f53b61e67c4cb5cd04c196d204 (diff) | |
| download | yosys-fa295a4528513d6beeff638520d519faafd99324.tar.gz yosys-fa295a4528513d6beeff638520d519faafd99324.tar.bz2 yosys-fa295a4528513d6beeff638520d519faafd99324.zip | |
Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index df0e94dcc..caadf1981 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -411,6 +411,7 @@ struct RTLIL::SigSpec { std::vector<RTLIL::SigBit> to_sigbit_vector() const; RTLIL::SigBit to_single_sigbit() const; static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); }; |