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| author | clairexen <claire@symbioticeda.com> | 2020-06-08 15:27:15 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-08 15:27:15 +0200 |
| commit | fbd0d8d5f0c4d1dc1fc35371adc6d89efd2534cd (patch) | |
| tree | 53480c2d71083790474ec7c70659f96874b77d60 /kernel/rtlil.h | |
| parent | f57524cf713e2cdc368ded8b7e13f85d310b8749 (diff) | |
| parent | 5a5a9b4ffe8b38eca7dc4fdfc56a16d401022fa2 (diff) | |
| download | yosys-fbd0d8d5f0c4d1dc1fc35371adc6d89efd2534cd.tar.gz yosys-fbd0d8d5f0c4d1dc1fc35371adc6d89efd2534cd.tar.bz2 yosys-fbd0d8d5f0c4d1dc1fc35371adc6d89efd2534cd.zip | |
Merge pull request #2105 from whitequark/split-flatten-off-techmap
Split `flatten` from `techmap` and simplify it
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 51e573e76..86b4e25b6 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1170,6 +1170,8 @@ public: RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); + RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other); + // The add* methods create a cell and return the created cell. All signals must exist in advance. RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); |