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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 10:05:42 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 10:05:42 +0200 |
| commit | 5b51b67297a5e5e20cbe2b015b584aee4c30489f (patch) | |
| tree | 934ce8ee55c3c58a1e2c11f19eec194665413906 /kernel/sigtools.h | |
| parent | c61467a32c4bd3ec4b9e0cb6d36d602f0e4dea81 (diff) | |
| parent | ec923652e2eb721aa16657e54a67666f855c3d65 (diff) | |
| download | yosys-5b51b67297a5e5e20cbe2b015b584aee4c30489f.tar.gz yosys-5b51b67297a5e5e20cbe2b015b584aee4c30489f.tar.bz2 yosys-5b51b67297a5e5e20cbe2b015b584aee4c30489f.zip | |
Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor
Diffstat (limited to 'kernel/sigtools.h')
| -rw-r--r-- | kernel/sigtools.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/sigtools.h b/kernel/sigtools.h index e93780b49..cd179ebf0 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -144,7 +144,7 @@ struct SigPool { RTLIL::SigSpec sig; for (auto &bit : bits) { - sig.append(RTLIL::SigSpec(bit.first, 1, bit.second)); + sig.append(RTLIL::SigSpec(bit.first, bit.second)); break; } return sig; @@ -154,7 +154,7 @@ struct SigPool { RTLIL::SigSpec sig; for (auto &bit : bits) - sig.append(RTLIL::SigSpec(bit.first, 1, bit.second)); + sig.append(RTLIL::SigSpec(bit.first, bit.second)); sig.sort_and_unify(); return sig; } |