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| author | whitequark <whitequark@whitequark.org> | 2020-04-10 01:24:31 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-10 01:24:31 +0000 |
| commit | 7c06cb615745fce4490c1d5b9dcf48d40fa00445 (patch) | |
| tree | c4ea87f2c84b59ece5da1701f4c9df61a2ac58d2 /kernel/yosys.h | |
| parent | 371af7da381e9d17e4475cb0599865f7bea5a632 (diff) | |
| parent | 4737f426ff20324316ab037cef719da4b5c520dd (diff) | |
| download | yosys-7c06cb615745fce4490c1d5b9dcf48d40fa00445.tar.gz yosys-7c06cb615745fce4490c1d5b9dcf48d40fa00445.tar.bz2 yosys-7c06cb615745fce4490c1d5b9dcf48d40fa00445.zip | |
Merge pull request #1562 from whitequark/write_cxxrtl
write_cxxrtl: new backend
Diffstat (limited to 'kernel/yosys.h')
| -rw-r--r-- | kernel/yosys.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/kernel/yosys.h b/kernel/yosys.h index 16e0aaf1c..6aed7c96a 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -207,6 +207,7 @@ namespace RTLIL { struct SigSpec; struct Wire; struct Cell; + struct Memory; struct Module; struct Design; struct Monitor; @@ -229,6 +230,7 @@ using RTLIL::Design; namespace hashlib { template<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {}; template<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {}; + template<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {}; template<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {}; template<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {}; template<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {}; @@ -236,6 +238,7 @@ namespace hashlib { template<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {}; template<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {}; + template<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {}; template<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {}; template<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {}; template<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {}; |