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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-29 16:06:27 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-29 16:35:13 +0200 |
| commit | 03c96f9ce7120adf1c9bab93485a3b4bf6493ae9 (patch) | |
| tree | c59b7586ba36ebc0dc1576337c882b44db5f8dc5 /kernel | |
| parent | 397b00252dc0c4af725614bd12fc299147ba8efa (diff) | |
| download | yosys-03c96f9ce7120adf1c9bab93485a3b4bf6493ae9.tar.gz yosys-03c96f9ce7120adf1c9bab93485a3b4bf6493ae9.tar.bz2 yosys-03c96f9ce7120adf1c9bab93485a3b4bf6493ae9.zip | |
Added "techmap -map %{design-name}"
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 5 | ||||
| -rw-r--r-- | kernel/rtlil.h | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 83bbd7b17..f864d88c0 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -219,6 +219,11 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) } } +RTLIL::Design::Design() +{ + refcount_modules_ = 0; +} + RTLIL::Design::~Design() { for (auto it = modules_.begin(); it != modules_.end(); it++) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e8d05e7e4..1f25542f3 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -352,11 +352,16 @@ struct RTLIL::Design std::map<RTLIL::IdString, RTLIL::Selection> selection_vars; std::string selected_active_module; + Design(); ~Design(); RTLIL::ObjRange<RTLIL::Module*> modules(); RTLIL::Module *module(RTLIL::IdString name); + bool has(RTLIL::IdString id) const { + return modules_.count(id) != 0; + } + void add(RTLIL::Module *module); RTLIL::Module *addModule(RTLIL::IdString name); void remove(RTLIL::Module *module); |