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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-21 13:49:00 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-21 13:49:00 +0100 |
| commit | 09471846c553855c43224ce32d855c46f4df5140 (patch) | |
| tree | 659fff2b882e2d7c54a5eaf72adeed2328d4ba64 /kernel | |
| parent | 84ced2bb8ee2e6498b53ae6cdb77930aa98affbb (diff) | |
| download | yosys-09471846c553855c43224ce32d855c46f4df5140.tar.gz yosys-09471846c553855c43224ce32d855c46f4df5140.tar.bz2 yosys-09471846c553855c43224ce32d855c46f4df5140.zip | |
Major improvements in mem2reg and added "init" sync rules
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 952cb5944..c8f6b370f 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -44,7 +44,8 @@ namespace RTLIL STp = 2, // edge sensitive: posedge STn = 3, // edge sensitive: negedge STe = 4, // edge sensitive: both edges - STa = 5 // always active + STa = 5, // always active + STi = 6 // init }; extern int autoidx; |