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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-24 04:46:36 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-24 04:46:36 +0200 |
| commit | 22ede43b3f5016784b2e22c0ea95b7f718d7598e (patch) | |
| tree | dfa6d5c20d3efa5dff08e19f7a9c8b3a6a5a5109 /kernel | |
| parent | 3a2c5357771df05f80bff55e8ab3e467308c57d1 (diff) | |
| download | yosys-22ede43b3f5016784b2e22c0ea95b7f718d7598e.tar.gz yosys-22ede43b3f5016784b2e22c0ea95b7f718d7598e.tar.bz2 yosys-22ede43b3f5016784b2e22c0ea95b7f718d7598e.zip | |
Small changes regarding cover() and check() in SigSpec
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 15 | ||||
| -rw-r--r-- | kernel/rtlil.h | 4 |
2 files changed, 9 insertions, 10 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ca8e9b6d8..5194b5f7d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1594,10 +1594,7 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const { - if (other) - cover("kernel.rtlil.sigspec.replace_other"); - else - cover("kernel.rtlil.sigspec.replace"); + cover("kernel.rtlil.sigspec.replace"); unpack(); pattern.unpack(); @@ -1797,8 +1794,7 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end()); width_ += signal.width_; - - check(); + // check(); } void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) @@ -1829,8 +1825,7 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) } width_++; - - check(); + // check(); } void RTLIL::SigSpec::extend(int width, bool is_signed) @@ -1881,9 +1876,9 @@ RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const return sig; } +#ifndef NDEBUG void RTLIL::SigSpec::check() const { -#ifndef NDEBUG if (packed()) { cover("kernel.rtlil.sigspec.check.packed"); @@ -1916,8 +1911,8 @@ void RTLIL::SigSpec::check() const assert(width_ == SIZE(bits_)); assert(chunks_.empty()); } -#endif } +#endif bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index c25f71855..68eee46ea 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -599,7 +599,11 @@ public: operator std::vector<RTLIL::SigChunk>() const { return chunks(); } operator std::vector<RTLIL::SigBit>() const { return bits(); } +#ifndef NDEBUG void check() const; +#else + inline void check() const { } +#endif }; inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const { |