Added $sop cell type and "abc -sop"

2 files changed, 36 insertions, 1 deletions

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 40fdca36e..41dd51ed8 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -85,7 +85,7 @@ struct CellTypes
 		std::vector<RTLIL::IdString> unary_ops = {
 			"$not", "$pos", "$neg",
 			"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
-			"$logic_not", "$slice", "$lut"
+			"$logic_not", "$slice", "$lut", "$sop"
 		};
 
 		std::vector<RTLIL::IdString> binary_ops = {
@@ -357,6 +357,32 @@ struct CellTypes
 			return t;
 		}
 
+		if (cell->type == "$sop")
+		{
+			int width = cell->parameters.at("\\WIDTH").as_int();
+			int depth = cell->parameters.at("\\DEPTH").as_int();
+			std::vector<RTLIL::State> t = cell->parameters.at("\\TABLE").bits;
+
+			while (GetSize(t) < width*depth*2)
+				t.push_back(RTLIL::S0);
+
+			for (int i = 0; i < depth; i++)
+			{
+				bool match = true;
+
+				for (int j = 0; j < width; j++) {
+					RTLIL::State a = arg1.bits.at(j);
+					if (t.at(2*width*i + 2*j + 0) == State::S1 && a == State::S1) match = false;
+					if (t.at(2*width*i + 2*j + 1) == State::S1 && a == State::S0) match = false;
+				}
+
+				if (match)
+					return State::S1;
+			}
+
+			return State::S0;
+		}
+
 		bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();
 		bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool();
 		int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1;
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index a706491e8..3b1df4406 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -845,6 +845,15 @@ namespace {
 				return;
 			}
 
+			if (cell->type == "$sop") {
+				param("\\DEPTH");
+				param("\\TABLE");
+				port("\\A", param("\\WIDTH"));
+				port("\\Y", 1);
+				check_expected();
+				return;
+			}
+
 			if (cell->type == "$sr") {
 				param_bool("\\SET_POLARITY");
 				param_bool("\\CLR_POLARITY");