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| author | Clifford Wolf <clifford@clifford.at> | 2014-01-17 16:34:50 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-17 16:34:50 +0100 |
| commit | 651ce67d979d355c53e9bf17b91b22368adca072 (patch) | |
| tree | 5efd0f52201c5b56e718b2db25f62e35649ba6a2 /kernel | |
| parent | f3154f569423c978946982a9ddb0a05627e255a9 (diff) | |
| download | yosys-651ce67d979d355c53e9bf17b91b22368adca072.tar.gz yosys-651ce67d979d355c53e9bf17b91b22368adca072.tar.bz2 yosys-651ce67d979d355c53e9bf17b91b22368adca072.zip | |
Added select -assert-none and -assert-any
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 504fdbbdc..e0b3a693d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -227,6 +227,9 @@ struct RTLIL::Selection { if (!full_selection && selected_modules.count(module->name) == 0) selected_members[module->name].insert(member->name); } + bool empty() const { + return !full_selection && selected_modules.empty() && selected_members.empty(); + } }; struct RTLIL::Design { |