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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 16:45:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 16:45:36 -0700 |
| commit | 6bf7114bbd4075c2761a478406e02d4b23742aab (patch) | |
| tree | 4e323b7f8e1389ac403e2729d72e0c2fb4d42a07 /kernel | |
| parent | 279fd22ddfe44a9ddd6504134d1029f6b7649149 (diff) | |
| download | yosys-6bf7114bbd4075c2761a478406e02d4b23742aab.tar.gz yosys-6bf7114bbd4075c2761a478406e02d4b23742aab.tar.bz2 yosys-6bf7114bbd4075c2761a478406e02d4b23742aab.zip | |
Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ded1cd60e..bd2fd91a3 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3554,6 +3554,12 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const if (width_ != other.width_) return false; + // Without this, SigSpec() == SigSpec(State::S0, 0) will fail + // since the RHS will contain one SigChunk of width 0 causing + // the size check below to fail + if (width_ == 0) + return true; + pack(); other.pack(); |