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author | Eddie Hung <eddie@fpgeh.com> | 2020-04-16 10:21:08 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
commit | 7812a2959b9b23b44e8144f9edb139f282d623e1 (patch) | |
tree | 9f986b9dc9f31dd9d57ab78116d46cc67c76cace /kernel | |
parent | 4cec21b93e62e9c43a0ab9618c0111ee65e520c1 (diff) | |
download | yosys-7812a2959b9b23b44e8144f9edb139f282d623e1.tar.gz yosys-7812a2959b9b23b44e8144f9edb139f282d623e1.tar.bz2 yosys-7812a2959b9b23b44e8144f9edb139f282d623e1.zip |
kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/timinginfo.h | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h index fb4e0930d..36908868c 100644 --- a/kernel/timinginfo.h +++ b/kernel/timinginfo.h @@ -128,11 +128,9 @@ struct TimingInfo int rise_max = cell->getParam(ID::T_RISE_MAX).as_int(); int fall_max = cell->getParam(ID::T_FALL_MAX).as_int(); int max = std::max(rise_max,fall_max); - if (max < 0) - log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell)); - if (max <= 0) { - log_debug("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell)); - continue; + if (max < 0) { + log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\n", log_id(module), log_id(cell)); + max = 0; } for (const auto &d : dst) { auto &v = t.arrival[NameBit(d)]; @@ -152,11 +150,9 @@ struct TimingInfo if (!c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst)); int max = cell->getParam(ID::T_LIMIT_MAX).as_int(); - if (max < 0) - log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell)); - if (max <= 0) { - log_debug("Module '%s' contains specify cell '%s' with T_LIMIT_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell)); - continue; + if (max < 0) { + log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\n", log_id(module), log_id(cell)); + max = 0; } for (const auto &s : src) { auto &v = t.required[NameBit(s)]; |