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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-10 07:16:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-10 07:16:30 +0200 |
| commit | 85287295b27dc3d51d2958dccb4f9098984b794a (patch) | |
| tree | 03d1517947ed1dc553e3cb1a765b785dc0014645 /kernel | |
| parent | 66f9ee412ae94fa305660bdc33fa0c00fedd5500 (diff) | |
| download | yosys-85287295b27dc3d51d2958dccb4f9098984b794a.tar.gz yosys-85287295b27dc3d51d2958dccb4f9098984b794a.tar.bz2 yosys-85287295b27dc3d51d2958dccb4f9098984b794a.zip | |
Fixed cellaigs port extending
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/cellaigs.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index b738b9dba..483aa7d57 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -77,7 +77,7 @@ struct AigMaker if (portbit >= GetSize(cell->getPort(portname))) { if (cell->parameters.count(portname.str() + "_SIGNED") && cell->getParam(portname.str() + "_SIGNED").as_bool()) return inport(portname, GetSize(cell->getPort(portname))-1, inverter); - return bool_node(!inverter); + return bool_node(inverter); } AigNode node; |