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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-05 18:04:19 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-05 18:04:19 +0200 |
| commit | a1c62b79d5d554be86b4b9bd53d72704b045acde (patch) | |
| tree | 5c163f9bf47b624c846ff6b1c42c955732963de7 /kernel | |
| parent | 95944eb69e45837516ff9c0cba54f77ab89af754 (diff) | |
| download | yosys-a1c62b79d5d554be86b4b9bd53d72704b045acde.tar.gz yosys-a1c62b79d5d554be86b4b9bd53d72704b045acde.tar.bz2 yosys-a1c62b79d5d554be86b4b9bd53d72704b045acde.zip | |
Avoid parameter values with size 0 ($mem cells)
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 6de5846f9..2dff53b7b 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -918,11 +918,11 @@ namespace { param("\\SIZE"); param("\\OFFSET"); param("\\INIT"); - param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS")); - param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS")); - param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS")); - param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS")); - param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS")); + param_bits("\\RD_CLK_ENABLE", std::max(1, param("\\RD_PORTS"))); + param_bits("\\RD_CLK_POLARITY", std::max(1, param("\\RD_PORTS"))); + param_bits("\\RD_TRANSPARENT", std::max(1, param("\\RD_PORTS"))); + param_bits("\\WR_CLK_ENABLE", std::max(1, param("\\WR_PORTS"))); + param_bits("\\WR_CLK_POLARITY", std::max(1, param("\\WR_PORTS"))); port("\\RD_CLK", param("\\RD_PORTS")); port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS")); port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH")); |