Merge pull request #1251 from YosysHQ/clifford/nmux

Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

7 files changed, 46 insertions, 9 deletions

diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc
index 26c625f89..fbc6d045e 100644
--- a/kernel/cellaigs.cc
+++ b/kernel/cellaigs.cc
@@ -325,6 +325,8 @@ Aig::Aig(Cell *cell)
 			int A = mk.inport("\\A", i);
 			int B = mk.inport("\\B", i);
 			int Y = mk.mux_gate(A, B, S);
+			if (cell->type == "$_NMUX_")
+				Y = mk.not_gate(Y);
 			mk.outport(Y, "\\Y", i);
 		}
 		goto optimize;
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 758661c02..d2594bc46 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -193,6 +193,7 @@ struct CellTypes
 		setup_type("$_ANDNOT_", {A, B}, {Y}, true);
 		setup_type("$_ORNOT_", {A, B}, {Y}, true);
 		setup_type("$_MUX_", {A, B, S}, {Y}, true);
+		setup_type("$_NMUX_", {A, B, S}, {Y}, true);
 		setup_type("$_MUX4_", {A, B, C, D, S, T}, {Y}, true);
 		setup_type("$_MUX8_", {A, B, C, D, E, F, G, H, S, T, U}, {Y}, true);
 		setup_type("$_MUX16_", {A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V}, {Y}, true);
diff --git a/kernel/consteval.h b/kernel/consteval.h
index 154373a8d..f70dfa0fb 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -145,7 +145,7 @@ struct ConstEval
 		if (cell->hasPort("\\B"))
 			sig_b = cell->getPort("\\B");
 
-		if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_")
+		if (cell->type.in("$mux", "$pmux", "$_MUX_", "$_NMUX_"))
 		{
 			std::vector<RTLIL::SigSpec> y_candidates;
 			int count_maybe_set_s_bits = 0;
@@ -175,7 +175,10 @@ struct ConstEval
 			for (auto &yc : y_candidates) {
 				if (!eval(yc, undef, cell))
 					return false;
-				y_values.push_back(yc.as_const());
+				if (cell->type == "$_NMUX_")
+					y_values.push_back(RTLIL::const_not(yc.as_const(), Const(), false, false, GetSize(yc)));
+				else
+					y_values.push_back(yc.as_const());
 			}
 
 			if (y_values.size() > 1)
diff --git a/kernel/cost.h b/kernel/cost.h
index 41a09eb63..e8e077ff5 100644
--- a/kernel/cost.h
+++ b/kernel/cost.h
@@ -24,10 +24,10 @@
 
 YOSYS_NAMESPACE_BEGIN
 
-int get_cell_cost(RTLIL::Cell *cell, dict<RTLIL::IdString, int> *mod_cost_cache = nullptr);
+int get_cell_cost(RTLIL::Cell *cell, dict<RTLIL::IdString, int> *mod_cost_cache = nullptr, bool cmos_cost = false);
 
 inline int get_cell_cost(RTLIL::IdString type, const dict<RTLIL::IdString, RTLIL::Const> &parameters = dict<RTLIL::IdString, RTLIL::Const>(),
-		RTLIL::Design *design = nullptr, dict<RTLIL::IdString, int> *mod_cost_cache = nullptr)
+		RTLIL::Design *design = nullptr, dict<RTLIL::IdString, int> *mod_cost_cache = nullptr, bool cmos_cost = false)
 {
 	static dict<RTLIL::IdString, int> gate_cost = {
 		{ "$_BUF_",    1 },
@@ -44,9 +44,33 @@ inline int get_cell_cost(RTLIL::IdString type, const dict<RTLIL::IdString, RTLIL
 		{ "$_OAI3_",   6 },
 		{ "$_AOI4_",   8 },
 		{ "$_OAI4_",   8 },
-		{ "$_MUX_",    4 }
+		{ "$_MUX_",    4 },
+		{ "$_NMUX_",   4 }
 	};
 
+	// match costs in "stat -tech cmos"
+	static dict<RTLIL::IdString, int> cmos_gate_cost = {
+		{ "$_BUF_",     1 },
+		{ "$_NOT_",     2 },
+		{ "$_AND_",     6 },
+		{ "$_NAND_",    4 },
+		{ "$_OR_",      6 },
+		{ "$_NOR_",     4 },
+		{ "$_ANDNOT_",  6 },
+		{ "$_ORNOT_",   6 },
+		{ "$_XOR_",    12 },
+		{ "$_XNOR_",   12 },
+		{ "$_AOI3_",    6 },
+		{ "$_OAI3_",    6 },
+		{ "$_AOI4_",    8 },
+		{ "$_OAI4_",    8 },
+		{ "$_MUX_",    12 },
+		{ "$_NMUX_",   10 }
+	};
+
+	if (cmos_cost && cmos_gate_cost.count(type))
+		return cmos_gate_cost.at(type);
+
 	if (gate_cost.count(type))
 		return gate_cost.at(type);
 
@@ -76,9 +100,9 @@ inline int get_cell_cost(RTLIL::IdString type, const dict<RTLIL::IdString, RTLIL
 	return 1;
 }
 
-inline int get_cell_cost(RTLIL::Cell *cell, dict<RTLIL::IdString, int> *mod_cost_cache)
+inline int get_cell_cost(RTLIL::Cell *cell, dict<RTLIL::IdString, int> *mod_cost_cache, bool cmos_cost)
 {
-	return get_cell_cost(cell->type, cell->parameters, cell->module->design, mod_cost_cache);
+	return get_cell_cost(cell->type, cell->parameters, cell->module->design, mod_cost_cache, cmos_cost);
 }
 
 YOSYS_NAMESPACE_END
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index a09f4a0d1..ba8472ec1 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1249,6 +1249,7 @@ namespace {
 			if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; }
 			if (cell->type == "$_ORNOT_")  { check_gate("ABY"); return; }
 			if (cell->type == "$_MUX_")    { check_gate("ABSY"); return; }
+			if (cell->type == "$_NMUX_")   { check_gate("ABSY"); return; }
 			if (cell->type == "$_AOI3_")   { check_gate("ABCY"); return; }
 			if (cell->type == "$_OAI3_")   { check_gate("ABCY"); return; }
 			if (cell->type == "$_AOI4_")   { check_gate("ABCDY"); return; }
@@ -1976,6 +1977,7 @@ DEF_METHOD_3(XnorGate,   "$_XNOR_",   A, B, Y)
 DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y)
 DEF_METHOD_3(OrnotGate,  "$_ORNOT_",  A, B, Y)
 DEF_METHOD_4(MuxGate,    "$_MUX_",    A, B, S, Y)
+DEF_METHOD_4(NmuxGate,   "$_NMUX_",   A, B, S, Y)
 DEF_METHOD_4(Aoi3Gate,   "$_AOI3_",   A, B, C, Y)
 DEF_METHOD_4(Oai3Gate,   "$_OAI3_",   A, B, C, Y)
 DEF_METHOD_5(Aoi4Gate,   "$_AOI4_",   A, B, C, D, Y)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 712250b3e..1cfe71473 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1154,6 +1154,7 @@ public:
 	RTLIL::Cell* addAndnotGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
 	RTLIL::Cell* addOrnotGate  (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
 	RTLIL::Cell* addMuxGate    (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = "");
+	RTLIL::Cell* addNmuxGate   (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = "");
 	RTLIL::Cell* addAoi3Gate   (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = "");
 	RTLIL::Cell* addOai3Gate   (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = "");
 	RTLIL::Cell* addAoi4Gate   (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = "");
@@ -1229,6 +1230,7 @@ public:
 	RTLIL::SigBit AndnotGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
 	RTLIL::SigBit OrnotGate  (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
 	RTLIL::SigBit MuxGate    (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = "");
+	RTLIL::SigBit NmuxGate   (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = "");
 	RTLIL::SigBit Aoi3Gate   (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = "");
 	RTLIL::SigBit Oai3Gate   (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = "");
 	RTLIL::SigBit Aoi4Gate   (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = "");
diff --git a/kernel/satgen.h b/kernel/satgen.h
index 210cca3f3..e9f3ecd44 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -475,7 +475,7 @@ struct SatGen
 			return true;
 		}
 
-		if (cell->type == "$_MUX_" || cell->type == "$mux")
+		if (cell->type == "$_MUX_" || cell->type == "$mux" || cell->type == "$_NMUX_")
 		{
 			std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
 			std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
@@ -483,7 +483,10 @@ struct SatGen
 			std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
-			ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), yy));
+			if (cell->type == "$_NMUX_")
+				ez->assume(ez->vec_eq(ez->vec_not(ez->vec_ite(s.at(0), b, a)), yy));
+			else
+				ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), yy));
 
 			if (model_undef)
 			{