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author | Clifford Wolf <clifford@clifford.at> | 2015-01-22 13:40:26 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-01-22 13:42:04 +0100 |
commit | a6aa32e762d29f050d0b6d49e288514964a5aac5 (patch) | |
tree | 57a49aeb765b1d9ec1b34d78b77d43a22645e5fd /kernel | |
parent | 0a225f8b273bfd036efa89f660114d4ab9cb190f (diff) | |
download | yosys-a6aa32e762d29f050d0b6d49e288514964a5aac5.tar.gz yosys-a6aa32e762d29f050d0b6d49e288514964a5aac5.tar.bz2 yosys-a6aa32e762d29f050d0b6d49e288514964a5aac5.zip |
Various equiv_simple improvements
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/satgen.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/kernel/satgen.h b/kernel/satgen.h index 2c69663c4..c874099b7 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -1163,6 +1163,25 @@ struct SatGen return true; } + if (cell->type == "$_BUF_" || cell->type == "$equiv") + { + std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep); + extendSignalWidthUnary(a, y, cell); + + std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; + ez->assume(ez->vec_eq(a, yy)); + + if (model_undef) { + std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + extendSignalWidthUnary(undef_a, undef_y, cell, false); + ez->assume(ez->vec_eq(undef_a, undef_y)); + undefGating(y, yy, undef_y); + } + return true; + } + if (cell->type == "$assert") { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); |