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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 15:58:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 15:58:01 -0700 |
| commit | cea7441d8ae7df8d22f510e6a101ec46a9d7751e (patch) | |
| tree | 8067ba09ecfaf6d9cf32e8ed9adba42be27b86a4 /kernel | |
| parent | c865559f9540c29cb9c6302edc8b4a2620c0b49d (diff) | |
| parent | bb2144ae733f1a2c5e629a8251bfbdcc15559aa4 (diff) | |
| download | yosys-cea7441d8ae7df8d22f510e6a101ec46a9d7751e.tar.gz yosys-cea7441d8ae7df8d22f510e6a101ec46a9d7751e.tar.bz2 yosys-cea7441d8ae7df8d22f510e6a101ec46a9d7751e.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.h | 2 | ||||
| -rw-r--r-- | kernel/yosys.cc | 4 |
2 files changed, 5 insertions, 1 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f4fcf5dcf..82cbfaf28 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1327,7 +1327,7 @@ public: #endif }; -struct RTLIL::CaseRule +struct RTLIL::CaseRule : public RTLIL::AttrObject { std::vector<RTLIL::SigSpec> compare; std::vector<RTLIL::SigSig> actions; diff --git a/kernel/yosys.cc b/kernel/yosys.cc index f95c0127b..a42a7c0b8 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -1273,6 +1273,10 @@ struct ScriptCmdPass : public Pass { log("If only one label is specified (without ':') then only the block\n"); log("marked with that label (until the next label) is executed.\n"); log("\n"); + log("In \"-scriptwire\" mode, the commands on the selected wire(s) will be executed\n"); + log("in the scope of (and thus, relative to) the wires' owning module(s). This\n"); + log("'-module' mode can be exited by using the 'cd' command.\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { |